Physical design: from RTL/Netlist to GDS2

Encore Semi has established a multi-expertise team to support Physical Design projects. We have executed on SoC implementation projects using Synopsys and Cadence tool suites in process, technologies down to 7nm.

  • CAD flow setup & optimization for back-end physical implementation
  • Synthesis/Timing analysis/Clock management (CDC, etc.)
  • DFT/DFx
  • Floor Planning – Place & Route
  • Performance analysis (Power, Signal Integrity, IR, etc.)
  • Timing closure

This environment allows for a broad flexibility in terms of how Encore Semi can support the projects of its customers.

We shape technical solutions aligned to customer’s context, desired design flow and tool set. Our team can support a complete flow, from RTL or Netlist to GDS2, or concentrate on providing support in specific areas.

Project Examples

Cellular Base Station SOC – Optimization of Chip-level Physical Design

  • Optimization of floorplan, synthesis and Place & Route to match system and packaging constraints of a complex SoC using a FinFET technology.
  • Very complex design with 4.62M Instance Counts after Initial Placement, a core density of ~80%, heavily RAM-dominant RLM area, with very few open standard cell areas and tight routing channels. 400MHz main clock, with some very long paths.
  • The RAMs grouping was reconfigured and RAMS were moved closer together and toward the outsides of the RLM
  • The logic was partitioned/regioned to get timing/congestion-critical modules into the available spaces between the RAMs