Design Implementation

Physical Design

Encore Semi’s physical design services are tool-agnostic. We typically work within and aligned to our customer’s CAD environment. Experience includes tools from Cadence, Synopsys, Mentor Graphics and more. Our involvement in state-of-the-art designs from the leading semiconductor companies gives us great exposure to advanced methodologies and flows for both low power designs and high performance designs. We master design flow automation to accelerate the design iterations, improve accuracy and assure on-time delivery. A lot of emphasis is put on optimizing floorplans to achieve best die size (PPA) under various constraints. Our physical design expertise spans across the entire RTL to GDSII task list, including timing analysis, power analysis, logic equivalency checking, signal integrity, OCV, DFM/DFT, LVS and DRC checks. The result is a manageable project with low risk and efficient physical implementation.

The expertise customers can rely on includes:

  • Logical and Physical Synthesis
  • Clock Tree Synthesis (H-Tree, partial H-Tree, custom mesh)
  • Timing Closure/(STA + SI)
  • Timing and Low Power Constraint (generation/validation of SDC, CPF/UPF, etc.)
  • Floorplan/Proto-tying (physical partitioning, critical route planning, and die estimation)
  • Power planning – (grid design and analysis)
  • Place & Route, (datapath/structured)
  • DRC/LVS check
  • Experience at chip, block and IP level
  • Low power design experience
  • Timing analysis and fixing
  • Voltage islands for power shut-off modes
  • Physical implementation of processor subsystems, structured logic and control logic
  • Experience with high speed interfaces & protocols (SerDes, PCIe, USB3, LPDDR4, etc.)
  • Large SoC methodology and scripting

Custom Layout

Encore Semi has a broad custom layout capability that includes production tape-outs, IP block layout, mixed signal functions, RF layout, and library collaterals. Depending on the targeted device, we work with various technologies (CMOS, FinFET, BiCMOS, PD-SOI, FD-SOI) from 130 nm down to 7 nm. Our Layout Designers are mastering a portfolio of layout techniques such as device matching, shielding, impedance matching, noise reduction, isolation, and many more. They have expertise in highly complex IP blocks including High Speed SerDes (up to 112 Gbps), mixed signal and RF components like PA, LNA, VCO, PLL, ADC, DAC, filters and ESD circuits, as well as standard cell layout and I/O’s for library collateral.


The Encore Semi Engineering organization is well positioned to assist with individual subject matter experts or a turn-key team-based solution. Using Encore Semi’s experience with a broad span of industry leading technologies, our DFT consultants have a great track record of success from DFT architecture/planning through implementation and post-silicon support.

  • Scan Insertion
  • ATPG Vector Generation
  • Test Compression techniques and tools
  • Stuck-AT, Transition, Path Delay, IDDQ test generation
  • Memory BIST
  • Logic BIST
  • JTAG Generation
  • RTL Level and gate-level simulation and verification
  • IEEE 1149.1, 1149.6 and 1687 implementations
  • Automotive Safety implementations (ISO 26262)

CAD and Design Enablement

A well-crafted Design Environment will increase productivity and produce more competitive products!

We support design implementation for a variety of IC process technologies, currently down to 7 nm FinFET, and our team is familiar with many of the Product Design Kits (PDKs) provided by the foundries companies, understanding their specific differences and particular ways of integrating within the CAD environment and the EDA tools.

Encore Semi has a large dedicated CADDesign Flow, and Design Enablement team, which is contributing to a variety of services, projects and solutions for our customers. With an average experience of 10 – 20 years per engineer, our client projects are accomplished using the latest technology and special attention to details to be able to design & deliver custom design environments that can produce SoC or IP Designs with outstanding performance, power, and cost parameters.

As part of its portfolio of services, Encore Semi can provide support for specific Design Enablement services and solutions such as tool evaluation, tool benchmarkingflow automationtechnology file generationtool correlationlibrary expansion and many others. We work at all levels of the design process, from Architecture, RTL generation, RTL verification, custom layout, synthesis, timing, Physical Design, or Physical Verification.