Design Correctness

Design Verification

The purpose of Functional Verification of Digital Design is to assure extensive coverage of complex designs, moving beyond the limits of simulation, detecting pre-silicon bugs and characterizing them for the design teams to implement corrections, with the ultimate goal or enabling first pass success of the silicon.

Encore Semi is maintaining and continuously expending a broad panel of expertise including:

  • Test/coverage strategy and testbench design
  • Development of commercial reconfigurable test-benches for complex licensed IP
  • Verilog/SystemC Design Verification – Unit (IP) and Integration Verification
  • Expertise with CPUs (ARM, x86, PowerPC), Memory Controllers (DDR), PCIe, high-speed interconnects (internal & external)
  • Simulation based verification (OVM/UVM Environments)
  • Assertions – “self-checking” for any testing
  • IP prototyping and validation firmware using emulation systems
  • Firmware/Hardware Co-Validation and Firmware Verification
  • Non-RTL based Firmware Verification techniques and system-level Firmware development acceleration

AMS Verification

A special emphasis is given to continuously expand our expertise in AMS verification for complex mixed-signal interfaces. The increase in complexity, configurability and programmability of the analog-to-digital interfaces, it is becoming critical for the design teams to perform thorough functional verification of these interfaces.

Mixed-signal verification is intended as part of integration sign-off, not a replacement to the analog verification done by the designers. Its primary focus is functional verification in time domain, in complement to the variation across PVT or the frequency response. Analog designers use in parallel the design/verification flow to verify circuit marginality and performance or to characterize the circuitry and parametrics.

AMS Verification techniques are usually based on all the best practices from digital verification: UVM, random vector generation and coverage driven verification. It builds one verification infrastructure, mixed with multiple coding style and netlist. (Verilog, SPICE, SystemVerilog, Verilog-AMS, Verilog-A).  Real Number Modeling can be used for maximum simulation performance in the event-driven simulators. AMS assertions are incorporated and metric-driven methodology is usually recommended.


Encore Semi can provide support to customers in leveraging emulation environments (typically “Big Box” Emulation tools – Veloce, Palladium, ZeBu), to extend beyond simulation limits for Complex Integration Verification

  • “Use Case” Validation without waiting for first silicon
  • Use of FPGA to Accelerate the FW/SW Development and System Validation
  • Design Reduction: emulate key structures to reduce/remap
  • ASIC-to-FPGA Remodeling – remodel clocks/memories
  • Partition/Mapping – partition and map to multi-FPGAs