Design tools, methodologies and automation

Encore Semi has a broad diversity of experts mastering most of the industry tools used to design various types of Integrated Circuits. This allows for RTL and IP design (front-end and back-end), SoC integration and verification, emulation and prototyping, RF/Analog IC design as well as firmware and software development.

This includes the mainstream tool suites from Cadence, Synopsys, Mentor Graphics, as well as proprietary tools from our historical customers. Some of our experts are more specialized in using particular tools and languages for power optimization, performance modeling, behavioral modeling, electromagnetic analysis or RF/S-parameter analysis.

Developing complex algorithms using tools such as Mathlab, and implementing it either on DSP or MCUs are tasks that Encore Semi engineers perform to support customer projects.

In order to help our customers set-up and optimize their design flows, Encore Semi has developed a solid expertise in various design methodologies. It spans from heterogeneous CAD flow set up, repository and release management, to the various approaches related to Design for Test (DFT). DFT and, more generally, DFx, has been a focused effort at Encore Semi, including DFT architecture, DFT planning, DFT design implementation and DFT data analysis. Various advanced techniques can be used to support customer projects, improving fault coverage and accelerating silicon production and yield.

  • Scan Insertion,
  • ATPG Vector Generation
  • Test Compression techniques and tools
  • Stuck-AT, Transition, Path Delay, IDDQ test generation
  • Memory BIST
  • Logic BIST
  • JTAG Generation
  • RTL Level and gate-level simulation and verification
  • IEEE 1149.1, 1149.6 and 1687 implementations

Combining DFT with Functional Safety implementations (ISO 26262) results in a unique ability for Encore Semi to develop efficient Design for Safety (DFS) strategies and implementation.

Part of our team is focused on design flow optimization and automation, making multi-language and cross-environment analysis possible. These engineers deeply understand the CAD environment and the configuration of the tools. They are experts at developing scripts and automation solutions, parsing data from one environment to another, enabling sophisticated analysis, correlation and optimization. This capability is critical when optimizing the power consumption of a complex SoC, while maintaining performance targets, for example.

When it comes to Functional Design Verification, Encore Semi remains at the forefront of technology, leveraging the UVM/OVM methodologies for both IP and chip-level verification, and using various simulation/verification toolsets (SNPS, CDN, Mentor), allowing a strong coverage-based and random stress approach, and developing sophisticated and thorough configurable Testbenches to achieve the expected coverage.