Encore Semi has developed a strong capability to perform efficient and complete integration of SoCs or ASICs. Customers are usually providing a specification, a micro-architecture, and the IP blocks to be integrated (Soft IP or Hard IP). Our engineering teams are developing the wrappers and glue-logic for each of the IP blocks, to match the micro-architecture and the specification. Chip-level functional verification is then performed after the assembly of all the IP blocks, to assure the targeted coverage. Test strategies and Testbenches are developed to stress all the configurations and dark corners of the design, tracking bugs as deep as possible. Advanced verification techniques are mastered, such as UVM/OVM, Formal, or emulation-based strategies.
When necessary, Encore Semi can develop and deploy a complete front-end methodology and flow to assure an efficient integration/verification of complex chips where multiple teams are concurrently contributing to the projects.
In addition, Encore Semi has developed a tool box allowing the automatic generation of RTL code for the glue-logic required to build wrappers around the various IP blocks. This tool box allows our engineers to significantly accelerate the integration process and save a lot of time to concentrate on the challenging parts of the integration/verification cycle.
This automation of RTL coding can be efficiently leveraged for both Chip-level Integration, as well as IP development. Massively speeding the up-front code generation reduces the overall coding effort and enables faster optimization by Logic Designers. Delivering a Functional Model sooner enables early verification start and accelerates the overall Front-End critical path.
The script-based tool box is optimized for repetitive common tasks. It supports various functions such as ARM AXI configurations and multiple connection techniques of the IPs to AXI fabrics. It allows for an automatic conversion of behavioral models to Synthesizable Verilog and provides a standard format for specifying state tables and configure a large library of modules.
After the targeted coverage is reached and all the uncovered bugs have been corrected by the design team, the final delivery is a verified RTL code that can be used as the starting point of the Physical Design implementation.
Typical Integration Project Phases
Phase 0 – Implementation Plan
- Definition of blocks, interfaces, product KPIs
- Specification of top-level RTL & Verification Environment
- Typical team – Tech Lead, RTL/Verification Senior experts (2-3 senior engineers)
Phase 1 – Initial Integration
- RTL – hook together IPs/blocks; enable major interfaces
- Verification – Top-level TestBench, Test Basic transactions
- Typical team – RTL (100%); Verification (50%-75%)
Phase 2 – Full Functionality
- RTL – complete coding of all functionality; including DFX features
- Verification – Stress all protocols; Coverage specification
- Typical team – RTL/Verification (100%)
Phase 3 – Final Closure/Iterate with design team
- RTL – Feedback from Synthesis/PD; Iterate based on KPI feedback from customer
- Verification – Finalize full test list; Obtain Full Coverage; Stress tests for bug hunt
- Typical team – RTL/Verification (100%)
Option 1 – Maintenance
- Post-RTL delivery to “back-end” design team & final customer
- Respond to additional Change Orders post design handoff (Phase 3)
- Extend beyond “tapeout” including participation in post-si debug
- Typical team – at least 1 Verification and 1 RTL engineer; typically more senior
Option 2 – Modularization/Base Design Definition
- Generalize design to be targeted for multiple customers and become a “base design” for future proliferations
- Enable quicker start-up of future designs using a similar baseline microarchitecture
- Alter & document RTL interfaces and Verification Environment/Testplan elements as:
- Fixed elements – difficult to change
- Flexible elements – areas to provide options for future family members
Option 3 – Auto/Functional Safety Compliance
- Leverage Encore Semi combined Verification & Auto/Functional Safety expertise
- Auto Safety Compliance often impacts RTL and Verification phases of an Integration project
HPC SoC – Full-chip verification
- Development of simulation-based and emulation-based verification platforms for a large High Performance Computing (HPC) SoC Design
- Many-core architecture with multiple high-speed, high-bandwidth interconnects.
- Full-chip verification including verification of multiple protocols (PCIe, DDR, SATA, etc.)
- Validation in the context of complex Power Management algorithms
- Verification of DFT/DFD features for servers (including RAS/CAS features)
ASIC – Integration flow development
- Optimization of an ASIC integration flow in a multi-design center context.
- Initial heterogeneous environment with multiple tools used in same project; Day-to-Day progress depending on tight communication (messaging, email, calls)
- Development of Revision Control/Repository tracking (prevent corruptions, enable debug & effective sharing), regression management (prevent new items (RTL or environment) from blocking team members) and Bug & Change tracking through a central communication not dependent on email, etc.; (prevent issues from being forgotten)