Encore Semi has put in place Centers of Expertise (CoEs) to support its customers for the optimization of Complex IP projects. Customers provide a reference RTL code of the IP (Soft IP), and possible associated hard-coded cells (Hard IP). Our engineers perform all the steps necessary to properly model, optimize and verify the IP, to make it ready for delivery to an integrator.
This can include Performance modeling, IP Synthesis, Timing Analysis, Power modeling and optimization, IP-level DFT/DFx, IP functional verification (UVM/OVM or other), as well as post-silicon validation & characterization of the IP when appropriate.
In support of this global activity, Encore Semi also provides support for Digital IP design, and can deliver specific RTL code, compliant to the customer-specified micro-architecture.
High-Speed Serdes IP – Static Timing Analysis
- FinFET – Timing verified against > 80 timing corners (mode * delay corner)
- Complex timing analysis and optimization of a highly-configurable High-Speed Serdes IP
- More than 10 functional blocks (RX, TX, PLL, JTAG, etc), interfacing to multiple analog macros
- 250+ clocks at top level, many more in the sub-blocks
- Using Tempus STA tool from Cadence
TCAM IP power optimization:
- Development of an innovative approach to analyze the search strategies in a TCAM IP, to optimize the power consumption and avoid power surges and power supply compression.
- Development of models resulting in an optimization of a skewed search approach to stagger the supply current requirements.
Custom IP for Set Top box – Low Power optimization
- Reduction of power of a custom IP design to meet the system requirements for low power
- Development of a method and internal mechanisms to monitor the activity on the die and adjust the power distribution and biasing in an optimum way.
DDR / LPDDR IP – Configurable testbench for SoC-level integration
- Development of a highly configurable testbench for a variety of DDR / LPDDR IPs
- Testbench used by the SoC integrators to verify the DDR IP at the chip/system-level, according to the selected configurations of the IP.
- Using UVM methodology
High Speed SerDes IP – Development of Mixed Signal Verification environment
- Development of a Mixed-Signal verification environment for systemic implementation of metric-driven verification for a family of a High-Speed SerDes IPs using an advanced FinFet technology.
- Development of real number modeling to enable Mixed-Signal (Digital <-> Analog) Verification in the logical environment using the Cadence AIUM mixed-signal flow.